How to add additional delay in selected path?

[Altera_Forum]

TimeQuest report that there exist a hold violation critical path, and the slack is -4ns. 

How can I add additional 4ns delay in the path without change the functionality? I have try to add four NOT gate, but it add less that 1ns delay.  Any suggestion?

[Altera_Forum]

Use LCEL's instead, while it is not a good practice do work this way unless there is realy NO other way.

[Altera_Forum]

Well you really should not have hold time issues in an FPGA. This is probably caused by unintentional clock skew in your design. But if the circuit really is what you want and is being analyzed as you desire, than you should check out:  

Assignment->Settings->Fitter Settings and make sure "Optimize hold timing" is set to "All paths". This will allow the fitter to add the data delay you need. You may also want to turn on "Optimize fast-corner timing.

[Altera_Forum]

Do you mean that if I check out: 

  --- Quote Start ---  Assignment->Settings->Fitter Settings and make sure "Optimize hold timing" is set to "All paths". This will allow the fitter to add the data delay you need. You may also want to turn on "Optimize fast-corner timing.  --- Quote End ---    Then the fitter will add delay when necessary, so that hold violation will never occur?

[Altera_Forum]

--- Quote Start ---  Do you mean that if I [use the Fitter setting] Then the fitter will add delay when necessary, so that hold violation will never occur?  --- Quote End ---    "Never" is too strong a description, but setting "Optimize hold timing" to "All paths" will make the Fitter attempt to prevent hold-time violations by inserting routing delay where the Fitter's timing estimates predict the additional delay is needed. The Fitter won't always estimate that timing correctly (exact timing analysis isn't done till the end of compilation), and the Fitter might give up if it thinks too much routing delay would be required.  Notice godfather's comment about clock skew. Before you use that Fitter setting, make sure your problem is not from clock skew caused by an avoidable reason like logic (a divide-by-n register, a clock mux, etc.) in the clock path. The Classic Timing Analyzer will show you clock skew if you do "list paths" on a failing path and expand the message lines until you find the clock skew portion with the clock path detail under that. When you run report_timing with TimeQuest, a clock skew number is reported, and you have the ability to show the detail in the clock path similar to "list paths" for the Classic Timing Analyzer.

[Altera_Forum]

Given your earlier threads about a divide-by-2 register, I suspect your present clock skew problem is for a cross-domain path with just the source or just the destination register using that divided clock. Recall the post I referred you to before at http://www.alteraforum.com/forum/showthread.php?p=2457#post2457 where the next-to-least-preferred option is this: "If you have hold violations going between domains, have the Fitter try to fix them by setting 'Optimize hold timing' to 'All paths'." 

 If you are not willing to change your divide-by-2 clock to a divide-by-2 clock enable (using the undivided clock) and can't use a PLL for the slower clock, then you might want to reconsider how you transfer data between clock domains. Maybe you can change to asynchronous transfers with handshaking if you are transferring a set of signals (like a bus) or use simple metastability synchronization registers if you are transferring data on individual signals that don't have to be synchronized to each other.

[Altera_Forum]

I encounter into Hold Violation, pls see the following pic: 

http://blogimg.chinaunix.net/blog/upfile2/080126152345.jpg   I have set "Optimize hold timing" to "All paths" and turn on "Optimize fast-corner timing, but failed.

[Altera_Forum]

Sorry I need the answer. 

The slack is so slim, the QuartusII fitter should optimize them, shouldn't it?