How to adjust bus width?

Altera_Forum · ‎07-19-2012

In my design, sometimes I need to adjust bus width such as:

wire [10:0] a;

wire [5:0] b;

assign b={a[10:9],a[3:0]};

I always program like this. But it seems in some design it will cause problem and there are some errors which I can't understand appear in ModelSim simulation.

I just wonder is there any other approaches to do bus width adjust which is better?

Thanks very much.

Altera_Forum · ‎07-19-2012

The syntax is correct. I used it in ModelSim, too, but I never had problems.

What do you mean with "some errors"? Compile or functional simulation?

Altera_Forum · ‎07-20-2012

Sorry Cris, actually I did not express exact. I just wonder whether this syntax may cause problem in static timing analysis? Based on my understanding, it should not since this is just connecting wire.

Altera_Forum · ‎07-22-2012

With functional simulation I indeed meant static timing analysis.

So the answer is still Yes: your syntax is correct. You probably have an error somewhere else.

Altera_Forum · ‎07-22-2012

Thanks very much, I will check.