How to allocate pins for Address/Control in DDR2 memory controller Megafunction.

[Altera_Forum]

Hi all, 

  I have generated a DDR2 Memory controller Mega Function. I Added all the design files needed to my project and tried to compile the design using Full design Flow. I actually want the QSF file with pin placements for all signals. But after Compilation I am just getting Placements for Data group only. Even I tried by running Auto_add_constraints Script but it is also just adding LOC constrainst to data only.    I assume it happened because I have selected the positions to place my data bytes in the constraints phase of IP Toolbench. Is there any similar way to select positions and allocate Address and other control signals too?    And When I opened the pin planner to view the placements of pins, pins are just allocated for Data. I can allocate other signals manually but I want the pin allocations done by fitter or pin planner. When I clicked on show fitter-assignments All signals are showing as allocated even Address and other control signals, but when pressed start I/O Analysis they are not getting updated in QSF. Can someone say why? And suggest me a way to get all the pin allocation done by Quartus II.    Sometimes tool is giving warning message as follows and its not coming when I allocate pins manually by dragging the signals on to the pins in pin planner. Kindly helpme.   Critical Warning: No exact pin location assignment(s) for 18 pins of 59 total pins  Info: Pin clk_to_sdram not assigned to an exact location on the device  Info: Pin clk_to_sdram_n not assigned to an exact location on the device  Info: Pin ddr_a[0] not assigned to an exact location on the device  Info: Pin ddr_a[1] not assigned to an exact location on the device  Info: Pin ddr_a[2] not assigned to an exact location on the device  Info: Pin ddr_a[3] not assigned to an exact location on the device  Info: Pin ddr_a[4] not assigned to an exact location on the device

[Altera_Forum]

you should assign them by yourself,and run the tcl