How to avoid delay

[Altera_Forum]

Hello everyone, 

 My problem is that i have an output available at a current clock cycle and i need to be read at the same clock cycle by another register.  My top level entity is where i instantiate components but the problem is exactly in this code :   library ieee;use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; use ieee.math_real.all; library std; use work.MIN.all; entity labeling is generic( LABEL_WIDTH : integer; PIX_WIDTH : integer ); port( clk_proc : in std_logic; reset_n : in std_logic; ------------------------- in flow ----------------------- in_data : in std_logic; in_fv : in std_logic; in_dv : in std_logic; p00u : in std_logic; p01u : in std_logic; p02u : in std_logic; p10u : in std_logic; p11u : in std_logic; p12u : in std_logic; ------------------------ out flow ----------------------- out_fv : out std_logic; out_dv : out std_logic; ------------------------ labels -------------------------- north_LABEL , west_LABEL : in std_logic_vector ((LABEL_WIDTH-1) downto 0); north_west_LABEL , north_ouest_LABEL : in std_logic_vector ((LABEL_WIDTH-1) downto 0 ); current_LABEL , Label_to_merge , Label_instead : out std_logic_vector ((LABEL_WIDTH - 1) downto 0); need_to_merge, need_to_resolve: out std_logic ; number_of_object : out natural ); end labeling; architecture arch of labeling is ------ ------------------signaux pour les étiquettes------------------------------------------------------------------------------- signal north ,west : integer :=0; signal north_ouest , north_west : integer:=0; signal curr : integer; signal L_to_merge , L_instead : integer:=0 ; signal merge , resolve : std_logic; ------------------------------------------------------------------------------------------------------------------------ Begin north <= to_integer ( signed( '0' & (north_LABEL))); west <= to_integer ( signed( '0' & (west_LABEL))); north_west <= to_integer ( signed( '0' & (north_west_LABEL))); north_ouest <= to_integer ( signed( '0' & (north_ouest_LABEL))); ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------- labeling--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- process(clk_proc,reset_n) variable new_label : integer:= 1 ; variable n_objects : integer := 0 ; begin if (reset_n = '1' )then curr <=0; elsif (rising_edge(clk_proc))then if ((in_fv and in_dv )='1' ) then if (in_data= '0')then curr <= 0; merge<='0'; else if (p01u = '1') then curr <= north; merge<='0'; else if (p02u='1') then if (p00u ='1') then merge <='1'; curr<= minimum(north_west,north_ouest); L_to_merge <= maximum (north_west,north_ouest); L_instead <= minimum(north_west,north_ouest); else if (p10u ='1') then merge <='1'; curr<= minimum(west,north_ouest); L_to_merge <= maximum(west,north_ouest); L_instead <= minimum(north_west,north_ouest); n_objects := n_objects - 1 ; else curr<= north_ouest; merge<='0'; end if; end if; else if (p00u ='1') then curr <= north_west; merge<='0'; else if (p10u ='1') then curr<= west; merge<='0'; else curr<= new_label; new_label:= new_label+1; n_objects := n_objects + 1 ; merge<='0'; end if; end if; end if; end if; end if; if (merge='1' and north_ouest=minimum(north_west,north_ouest)) then resolve<='1'; else resolve<='0'; end if; if merge='1' then n_objects := n_objects - 1 ; end if; end if; end if; report "The number of objects is " & integer'image(n_objects); number_of_object<=n_objects; end process; --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ current_LABEL <= std_logic_vector(to_signed(curr,LABEL_WIDTH)); Label_to_merge<= std_logic_vector(to_signed(L_to_merge,LabEL_WIDTH)); Label_instead<= std_logic_vector(to_signed(L_instead,LabEL_WIDTH)); need_to_merge<=merge; need_to_resolve<= '1' when merge='1' else '0'; end arch;  Where the signal current_LABEL takes always the previous values of North, North_ouest, North_est and west instead of the current values .  Ps: The North, North_ouest, North_Est and West values are provided by another module.

[Altera_Forum]

I dont think I really follow what the problem is. Do you just want an unregistered output?

[Altera_Forum]

Here is a screenshot for the waveform of my top level entity  

 In the second clock cycle q_labelling ( corresponding to the current_Label signal of the above code ) must take the qd (west in the code) of the same clock cycle but instead it takes the previous value.

[Altera_Forum]

I'am simply looking for reading a value in a module during writing it from another module. Is that even possible?

[Altera_Forum]

Anything is possible 

Why not just pass the data through without registering it? or just produce the data in parallel. did you draw a circuit diagram before writing the code'?

[Altera_Forum]

Yes i did otherwise i wouldn't be able to write anything. But could you please explain it to me how is it possible to just pass the data without registering it ?

[Altera_Forum]

Yes - do the calculations in an unclocked process. But be aware that this may decrease your fmax. 

 Why not simply register the output of the other module?

[Altera_Forum]

Yes i did try to omit the process and do the caclculation but the result got worsened. About register the output , in fact the output of the first module is the input of the second one and the output of the second module is the input of the first one. And it must be like that unfortunately..

[Altera_Forum]

Here is exactly what i'm implementing  

https://www.alteraforum.com/forum/attachment.php?attachmentid=13026 .  The Lx is provided by another module and the calculation of Lx depends on the four registers LA to LD .

[Altera_Forum]

Just pass lx in to generate la to ld and also delay lx separately

[Altera_Forum]

I am sorry i'm newbie to vhdl what's exactly to generate why did you choose it as solution exactly ?

[Altera_Forum]

FPGAs are good at parrellel logic. If you need Lx at different places, then create copies of it.

[Altera_Forum]

Thank you so much for your help.