Hello, I'm new to verification process in VHDL. I need to verify a custom Avalon-MM slave component. What I did so far is the following: I generated a testbench system in Qsys and now I have tb file generated. This file contains component declarations of master BFM, clock and reset sources and my component. As I understand, now I need to write custom test calling master BFM procedures. I don't know how to do this. It would be nice if somebody could point me to a VHDL example, as I have troubles finding one.