Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to call Avalon-MM Master BFM API procedures in VHDL


Hello, I'm new to verification process in VHDL. I need to verify a custom Avalon-MM slave component. What I did so far is the following: I generated a testbench system in Qsys and now I have tb file generated. This file contains component declarations of master BFM, clock and reset sources and my component. As I understand, now I need to write custom test calling master BFM procedures. I don't know how to do this. It would be nice if somebody could point me to a VHDL example, as I have troubles finding one.


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