Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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17268 Discussions

How to compansate external phase-shift

Altera_Forum
Honored Contributor II
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I have CycloneIII on the board. Some synchronios signals come through the board to CycloneIII with phase shifts. Can these shifts be compensated in QuartusII for CycloneIII?

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Altera_Forum
Honored Contributor II
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If you've properly entered timing constraints, and instructed the fitter to optimize hold timing, the fitter ought to be able to add delay to compensate for the phase shift. You'll need to specify the input delay for each individual signal. I assume these are regular I/O signals.  

 

There are of course other methods. You could create a PLL with multiple outputs at different phases for sampling your input signals. You would then have to resynchronize these to a common clock domain. 

 

Jake
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Altera_Forum
Honored Contributor II
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Ok. It works. Thanks. The only strange thing is why Altera not remomeds to "combine individual or global tSU, tH, tPD, tCO, minimum tCO, or minimum tPD assignments with Input Delay or Output Delay assignments".

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