How to constrain generated clks derived from other generated clks?

[Altera_Forum]

Hi Everyone! 

 I am writing constraint for a legacy project. The original design uses too many "ripple clocks" that are generated from counters and FSMs. And the problem is while it is straightforward to constrain the first level of generated clocks, it is confusing to write constraints for the second level of generated clocks, that are "generated clocks derived from other generated clocks".  I have read Brad's post of "ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks (http://www.alteraforum.com/forum/showthread.php?p=8501)". It is really helpful. And I followed the instructions to reduce the number of the "ripple clocks" but there are still several ones left that are not easy to replace with clock enables. So I am determined to live with the remaining "ripple clocks" and constrain them correctly.  I have read the examples for create_generated_clock command in the Altera website and related docs. They have not mentioned about the second level of generated clocks. So I tried to constrain them like this:  create_clock -period 10.000 -name base_clk [get_ports clk_in]  create_generated_clock -name gen_clk_level_1   -source [get_ports clk_in]   -divide_by 2 -multiply_by 1   -master_clock [get_clocks base_clk]   [get_registers inst1]  create_generated_clock -name gen_clk_level_2   -source [get_registers inst1]   -divide_by 2 -multiply_by 1   -master_clock [get_clocks gen_clk_level_1]   [get_registers inst3]  This works for me. The compilation result is good.    But later on I read a doc from Synopsys about this kind of clock generation and it says:"generated clocks derived from other generated clocks should always be traced back to their non-generated source". And the suggested constraint for the above example looks like this:  create_clock -period 10.000 -name base_clk [get_ports clk_in]  create_generated_clock -name gen_clk_level_1   -source [get_ports clk_in]   -divide_by 2 -multiply_by 1   [get_registers inst1]  create_generated_clock -name gen_clk_level_2   -source [get_ports clk_in]   -edges {3 7 11}   [get_registers inst3]  This works too.  There is no difference in the constraint for the first level generated clock. So my questions are: 1. Can anyone tell me which style is correct?  2. For the second level generated clock, Does the first style accounts for all the clock source delay traced back to clk_in?

[Altera_Forum]

Attached is the source file and the constraint file.

[Altera_Forum]

Here comes the 3rd question which is found in a similar design: When a regiser is declared as the target of a generated clock, all the timing paths from this register is analyzed with this generated clock, even though some paths are not driven by this generated clock and should be analyzed as a timing path of the master clock domain. 

 The example is attached. Run the following command and the problem shows.  report_timing -from [get_keepers {inst1}] -to [get_keepers *counter_reg_bit*]  -setup -npaths 100 -detail path_only -panel_name {Report Timing}   The report says the path is analyzed between gen_clk_level_1 and its master clock base_clk. Actually this path should be analyzed in the base_clk domain only.  I tried to add a specific false path as the following  set_false_path -from [get_clocks gen_clk_level_1] -to [get_clocks base_clk]  -through [get_nets inst1]  but this eliminates the actual path -from [get_clocks base_clk] -to [get_clocks base_clk] too.   I know it is a bad coding style to use "ripple clocks", but as I mentioned in the top post I have to deal with it since it is "legacy".  Can anyone show me how to constrain and analyze this timing path under this situation? Or is this an inability of the TimeQuest?  BTW, I really love this STA tool. Many thanks in advance!!!

[Altera_Forum]

It seems I chose the wrong timing to post my thread. No one answered my question execpt myself. Can anyone help me with these questions. I really need to constrain this design correctly. 

Many Thanks again in advance.