LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CHAR_7SEG IS
PORT ( c : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6));
END CHAR_7SEG;
ARCHITECTURE behaviour4 OF CHAR_7SEG IS
BEGIN
case c is
WHEN 000 =>
HEX0 <="76" ;
WHEN 001 =>
HEX0 <= "79";
WHEN 010=>
HEX0 <= "38";
WHEN 011=>
HEX0 <= "38";
WHEN 100=>
HEX0 <= "3F";
WHEN OTHERS =>
HEX0 <= "00";
END case;
END behaviour4; THE ERROR SHOWING IS ---->> Error (10500): VHDL syntax error at CHAR_7SEG.vhd(22) near text "case"; expecting ";", or an identifier ("case" is a reserved keyword), or "architecture" . HOW TO CORRECT THIS ERROR??
