How to create delay cell

[Altera_Forum]

I am trying to create a frequency doubler using an Xor and a DFF. However it requires a delay cell to create finite pulse width for the signal. I am using functional sim. Does the cell exist in the library? if not, how do I generate one? 

 I need to be more precise in my question. I can edit the VHDL file and add the "after" command". How do I ensure that Quarta II will synthesize the delay properly? Unfortunately I have given up on the timing simulation after three days. A veteran of FPGA commented earlier that it is easier to build the design than spend time on timing. So i plan to go that route. However that does not solve my delay question. Thanks for your help.

[Altera_Forum]

.. the design software allow use PLL block. How to questions described in "clocking and PLL User Guide". 

the VHDL 'after' construct only for sim. you should take lessons for digital schematic to build your own PLL )) just delay the input clock for 1/4 of period

[Altera_Forum]

My Question is Why? 

using logic to create clocks is never going to be very stable or reliable as they are affected alot by P&R and PVT. So even when you lock the logic to specific cells you will still get variations in the output frequency and skew.  The after command is a simulation only contruct. To put in a delay cell you will have to manually instantiate a cell, and then ensure the synthesis does not optimise the design. And then you will probably need to place it manually to tweak the correct frequency. This could be rather time consuming, and will then probably be affected if you change the design as the routing resources are changed.  Altera provides the LCELL Primitive for this function: http://quartushelp.altera.com/15.0/mergedprojects/hdl/prim/prim_file_lcell.htm  But you could save yourself all the pain by just using a PLL and setting the multiplier to x2