How to do synthesis with Synopsys design compiler?

Altera_Forum · ‎10-26-2015

Hi,

I would like to know how I can use the Synopsys design compilers to do synthesis for a specific Verilog module?

The primary reason is to do register re-timing. The physical register re-timing at fitting processing does not do much according to the fitter report, and I would like to do the design compilers for it.

I am using Quartus 13.1. And the Synopsys tools are licensed on another machine than what I am using for the Quartus.

So what should I do to make it work? Like where are the library files that I need to load? I know that I can generate netlists of ipblocks for other EDA tools to use, but do I need to load other libraries?

Should I just use the syn.v, the netlist file created by Design Compiler as a source code, or is there anyway to import it as a design partition file, and how should I create this partition if possible?

I would appreciate it if someone could give me a guidance or redirect me to an existing one.

Thanks!

Tie

Altera_Forum · ‎10-26-2015

Instead of using design compiler, you need synplify for FPGA fabric. Although theoretically Design compiler could work with library cells, it doesn't know about the LUT's of FPGA's. So it wouldn't do as good of a job.

Synopsys bought Synplicity a few years ago. Before that they had a tool called FPGA Compiler that was based on Design compiler, but it didn't do as well as synplicity's synplify pro.

Pete