Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to enable pull-up of IOs?

Altera_Forum
Honored Contributor II
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Hi, 

I want to enable the weak pull-ups of the I/Os. Is it possible to enable those using verilog code itself? Is it possible to enable the weak pull-up via programmable control bit from design? 

 

Thanks, 

Suby
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Altera_Forum
Honored Contributor II
1,564 Views

Pin features like current strength or pull-up enable can be only set at compile time.

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Altera_Forum
Honored Contributor II
1,564 Views

Thanks. Would you please let me know how can I set the pull_up enable? Can it be programmable based on the design register settings?

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Altera_Forum
Honored Contributor II
1,564 Views

I think I am going crazy. I have the same problem, except I have done it many times before. 

 

I thought is was meant to be done in a column in the Pin Planner tool (found under Assignments menu). Now I see there is no column for this. Did it disappear from the tool somehow? I am using Quartus II version 12.0 SPII and Cyclone IV. 

 

Someone please help! Restore our sanity!
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Altera_Forum
Honored Contributor II
1,564 Views

In the pin planner, right click in the pin list area. There from the context menu, select "Customize columns" and you'll be able to enable back the weak pull-up column.

Altera_Forum
Honored Contributor II
1,564 Views

Thanks Daixiwen. So I have gone crazy! How did I miss that? 

 

Anyway, now we know. About the pins, that is. 

 

SlowClock.
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