RAM inference for shift registers can be controlled by global synthesis options and individually for design entities and signals by synthesis attributes.
The Quartus software handbook gives this example how to specify "logic"-ramstyle (don't use embedded RAM) for a register array, it should work in a similar way for shift registers.
type memory_t is array (0 to 63) of std_logic_vector (0 to 7);
signal my_ram : memory_t;
attribute ramstyle : string;
attribute ramstyle of my_ram : signal is "logic"; Another example disables auto shift register recognition for the whole entity
entity my_entity is
-- Declare generics and ports
end my_entity;
architecture rtl of my_entity is
attribute altera_attribute : string;
-- Attribute set on architecture, not entity
attribute altera_attribute of rtl: architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
begin
-- The architecture body
end rtl; Of course all synthesis attributes can be set in the assignment editor as well.
