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I have a DE2-70 dev kit and would like to set up a couple of internal RAM 2D bit arrays. I will NOT be using SOPC/Qsys but would like to access these in Verilog. I have looked up the correct way to build a 2D array using reg [117:0] array_name [27:0]; for example. When I compile it using Quartus II 11 sp1 I do not get any usage on the memory bits on the chip. Am I missing something?
According to a previous piece of information I found there is a technique to force usage of internal RAM, but I cannot find an actual recipie for doing this. Any assistance would be much appreciated. Thanks, GeofLink Copied
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Quartus will use internal RAM for an array of that size if not instructed otherwise, but only if your code accesses the data in a way that allows RAM usage. If you read the compilation messages thoroughly, you'll find a warning if no RAM can be inferred.
The conditions for RAM inference are explained in the Quartus software handbook, design templates can be accessed in the context menu of the Quartus editor.- Mark as New
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Thank you for your reply. A quick question for you. Should the compilation report show that memory bits are used? If so, there is no indication that RAM is being allocated for anything. Also I have tried using this approach:
(* ramstyle = "M4K" *) reg [7:0] current [7:0]; to allocate a 64 bit array in RAM. No indication that has been successful either. Perhaps I need to use the megafunction wizard? Thanks for your assistance. Regards, Geof- Mark as New
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I have tried to find the section you reference in the Quartus software handbook version 12.0, but am unable to do so. Perhaps you could give me a section subheading or page number?
Also there were no warnings that RAM usage could not be inferred. I apologize for missing things that should be obvious. Regards, Geof FLASH: I did find the templates! I will try taking a look at those next.- Mark as New
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try:
settings -> Alalysis&Synt. -> More Settings -> Allow Any Ram Size for Recognition j.a
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