Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15044 Discussions

How to handle "_ver" suffix to Altera Verilog libraries? Other source files have hardcoded "use library" with names without that "_ver" suffix

ARach7
Beginner
255 Views

If user revert to Verilog, the Verilog flavor of CycloneV will be parsed. The names of the various altera Verilog libraries all get a “_ver” suffix.

The VHDL libraries do *not* have such suffix.

The result is that when some other VHDL entities have hardcoded “use library” statements, they reference libraries that no longer exists (as we chose Verilog).

This yield elaboration errors, as the VHDL code reference libraries that are not present.

0 Kudos
2 Replies
JoanneSinY_L_Intel
95 Views

Hi Arach,

 

Please refer to pdf below pg96. It mentions by specifies the device family which you are compiling the library, it will result in the compilation of all libraries required for RTL and gate level sim

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/manual/tclscriptrefmnl.pdf

 

 

Thanks

Joanne

 

JoanneSinY_L_Intel
95 Views
Hi Arach, May I know any update or should I consider that case to be closed? Thanks Joanne
Reply