If user revert to Verilog, the Verilog flavor of CycloneV will be parsed. The names of the various altera Verilog libraries all get a “_ver” suffix.
The VHDL libraries do *not* have such suffix.
The result is that when some other VHDL entities have hardcoded “use library” statements, they reference libraries that no longer exists (as we chose Verilog).
This yield elaboration errors, as the VHDL code reference libraries that are not present.
Please refer to pdf below pg96. It mentions by specifies the device family which you are compiling the library, it will result in the compilation of all libraries required for RTL and gate level sim