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ARach7
Beginner
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How to handle "_ver" suffix to Altera Verilog libraries? Other source files have hardcoded "use library" with names without that "_ver" suffix

If user revert to Verilog, the Verilog flavor of CycloneV will be parsed. The names of the various altera Verilog libraries all get a “_ver” suffix.

The VHDL libraries do *not* have such suffix.

The result is that when some other VHDL entities have hardcoded “use library” statements, they reference libraries that no longer exists (as we chose Verilog).

This yield elaboration errors, as the VHDL code reference libraries that are not present.

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Hi Arach,

 

Please refer to pdf below pg96. It mentions by specifies the device family which you are compiling the library, it will result in the compilation of all libraries required for RTL and gate level sim

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/manual/tclscriptrefmnl.pdf

 

 

Thanks

Joanne

 

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Hi Arach, May I know any update or should I consider that case to be closed? Thanks Joanne
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