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Valued Contributor III
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How to improve compilation process on Quartus II Web Edition

Dear sirs. First of all, thank you for your time. 

 

 

I am using Quartus II Web Edition 15.0 and the time of compilation it is about 3 minutes with a simple code example. I am using Windows 7 (64 bits) on a PC with 8G RAM and AMD A8 5500B APU processor. 

 

This compilation time it is normal for this configuration or it is possible to improve. 

 

 

 

Thanks 

Fabio Bairros
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Valued Contributor III
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Get more RAM. However, 3 minutes is already quick - you're clearly compiling a small design. Compile times for larger designs in large devices will take hours. Then it's worth putting in some effort to reduce compilation time. 

 

Cheers, 

Alex
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Valued Contributor III
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At least 16GB or preferably 32GB of DRAM (to act as disk buffer storage). A fast SSD or PCIE disk will also make a big difference. 

 

I have a Win7 64b XEON with 8 cores (altho the web edition does not use more than 2 cores IIRC) and 64GB of DRAM and a 1GB hybrid flash / magnetic disk. 

 

On a reasonably complex Cyclone IV design under web 16.0 it takes 2:35 start of compile to end of bit config file generation.
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Valued Contributor III
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3 minutes! I envy you. 

12 core Xeon, 128GB ram takes 6 hours for a stratix 4 (that has many clock domains and is very full). 

 

Ram is the biggest bottleneck. Then CPUs and hard disk.  

Sometimes you just have to wait!
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Valued Contributor III
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Interesting doc to read (for v15, but probably still applies to v16): https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/rn/rn_qts_dev_support.pdf 

 

How much host memory is recommended for various target FPGA devices.
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