How to include Component Declaration Files (.cmp)

[Altera_Forum]

Hello, 

 Can anyone tell me how to use the component declaration file generated by the Quartus IP catalog tool in another file? ( have been writing AHDL for many years but I am new to VHDL).  As an example I have a component shiftcounter and the IP tool generates a file shiftcounter.cmp including the following:  component shiftCounter  PORT  (clk_en : IN STD_LOGIC ;  clock : IN STD_LOGIC ;  cnt_en : IN STD_LOGIC ;  data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);  sclr : IN STD_LOGIC ;  sload : IN STD_LOGIC ;  q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  ); end component;  At the moment I keep copy & pasting this into the VHDL files that use that component but I'm sure there must be a way to "include" it. Any clues, please?  Thanks.

[Altera_Forum]

--- Quote Start ---  Hello,  Can anyone tell me how to use the component declaration file generated by the Quartus IP catalog tool in another file? ( have been writing AHDL for many years but I am new to VHDL).  As an example I have a component shiftcounter and the IP tool generates a file shiftcounter.cmp including the following:  component shiftCounter  PORT  (clk_en : IN STD_LOGIC ;  clock : IN STD_LOGIC ;  cnt_en : IN STD_LOGIC ;  data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);  sclr : IN STD_LOGIC ;  sload : IN STD_LOGIC ;  q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  ); end component;  At the moment I keep copy & pasting this into the VHDL files that use that component but I'm sure there must be a way to "include" it. Any clues, please?  Thanks.  --- Quote End ---    it is meant for copy/paste in a top level vhdl that wants to instantiate it. It is good for those of us lazy enough not to copy/paste from entity interface then just changing "entity" word to "component"

[Altera_Forum]

--- Quote Start ---  it is meant for copy/paste in a top level vhdl that wants to instantiate it. It is good for those of us lazy enough not to copy/paste from entity interface then just changing "entity" word to "component"  --- Quote End ---    So is there a simple way to have a file with a component declaration in it that I can include in other files where the component is used? If I use the component in 5 different files, I don;t really want to have to edit the same info in each file. Or is that complicated in VHDL?  Maybe I'm confusing my terminology because I'm relatively new to VHDL (I used AHDL for decades) but the concept of what I want to achieve seems simple. Just like including a header file containing a typedef in C. How do I do that?

[Altera_Forum]

--- Quote Start ---  So is there a simple way to have a file with a component declaration in it that I can include in other files where the component is used? If I use the component in 5 different files, I don;t really want to have to edit the same info in each file. Or is that complicated in VHDL?  Maybe I'm confusing my terminology because I'm relatively new to VHDL (I used AHDL for decades) but the concept of what I want to achieve seems simple. Just like including a header file containing a typedef in C. How do I do that?  --- Quote End ---    use declare component in a library and call the library without need to copy paste

[Altera_Forum]

you can use direct instantiation without adding component declaration. 

No need for component declaration if you do not want to use "configure" option in VHDL.

[Altera_Forum]

Thanks - that seems to work. I now only have to paste any updated component definition into the library once.