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I have project with Qsys and custom IP
IP has main Verilog file comm_channel_control.sv with lines
module (...)
...
`include "comm_channel_control_params.svh"
...
endmodule
main module and "comm_channel_control_params.svh" are in the folder $PROJECT_FOLDER/ip/comm_channel_control/
Analysis&Synthesis says
Error (10054): Verilog HDL File I/O error at comm_channel_control.sv(45): can't open Verilog Design File "comm_channel_control_params.svh"
How can I use `include in sources of ip ?
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Solved,
"Component Editor" window -> "Files" tab -> "Add File..."
Add files to include
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Thanks for sharing the solution, Which will help the community.

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