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EIbra
Novice
214 Views

How to `include file in the IP Verilog source?

I have project with Qsys and custom IP

 

IP has main Verilog file comm_channel_control.sv with lines

module (...) ... `include "comm_channel_control_params.svh" ... endmodule

main module and "comm_channel_control_params.svh" are in the folder $PROJECT_FOLDER/ip/comm_channel_control/

 

Analysis&Synthesis says

Error (10054): Verilog HDL File I/O error at comm_channel_control.sv(45): can't open Verilog Design File "comm_channel_control_params.svh"

 

 

How can I use `include in sources of ip ?

0 Kudos
2 Replies
EIbra
Novice
58 Views

Solved,

"Component Editor" window -> "Files" tab -> "Add File..."

Add files to include

AnandRaj_S_Intel
Employee
58 Views

Thanks for sharing the solution, Which will help the community.

 

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