Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15465 Discussions

How to `include file in the IP Verilog source?

EIbra
Novice
366 Views

I have project with Qsys and custom IP

 

IP has main Verilog file comm_channel_control.sv with lines

module (...) ... `include "comm_channel_control_params.svh" ... endmodule

main module and "comm_channel_control_params.svh" are in the folder $PROJECT_FOLDER/ip/comm_channel_control/

 

Analysis&Synthesis says

Error (10054): Verilog HDL File I/O error at comm_channel_control.sv(45): can't open Verilog Design File "comm_channel_control_params.svh"

 

 

How can I use `include in sources of ip ?

0 Kudos
2 Replies
EIbra
Novice
210 Views

Solved,

"Component Editor" window -> "Files" tab -> "Add File..."

Add files to include

AnandRaj_S_Intel
Employee
210 Views

Thanks for sharing the solution, Which will help the community.

 

Reply