How to make a rtl simulation of design using megafunctions

[Altera_Forum]

Hi, I am simulating with "ModelSim SE-64 10.2a" a design made in "Quartus II 64-bit 13.1.0" for a stratix V device 

 The design includes some Altera megafunctions generated with megafuncion wizard as scfifo, lpm_mux, lpm_compare and some other stuff . The design was being simulated in gate-level mode sucessfully, a big .who file with all blocks was generated in the gate_work directory and the simulation goes fine. Now I need to include my design in a global project which is being simulated in rtl mode.  The problem I have found is that when I try to simulate my project in rtl mode only lpm_mux and lpm_compare blocks are generated, neither the scfifo nor the other blocks I have in the design are compiled.  (How) can I perform the rtl simulation of a megafunciton as scfifo?

[Altera_Forum]

have you included all of the generated files in your larger project? 

how are you simulating? are you using quartus or have you written a .do file for the compilation? same question as above - have you included all the source files in your larger .do file to ensure vcom is run on the larger project.  have you compiled everything into the correct libraries?   what errors are you getting?  simulating in gate mode - bleugh - best avoid at all costs...

[Altera_Forum]

Thanks for your fast response Tricky. 

I am still tryng to be able to simulate my local project/design in rtl mode before including it in the large one, as up to now I was only able to simulate it in the gate level. I am launching the simulation from quartus in the same (small) project, changing the quartus compiling flow in the task window: Analysis->Fitter->TimeQuest->Netlist->Gate Level Simulation OR Analysis->RTL Simulation. Two different .do files (attached) are generated by quartus and compiled by the simulator. While in the gate level the top hierarchy block, DCFIFO.vho, is created and I know how to access the input/output ports, in the rtl mode only lpm_mux and lpm_compare blocks are compiled...  I expeted quartus do all the job for each simulation flow (libraries, etc) but it seems i have to say quartus to start the rtl simulation from the top hierarchy block?

[Altera_Forum]

You will be better off in the long term (IMO) learning to use modelsim yourself. 

a .do file is just a TCL file (ie. list of commands) for modelsim to run:  vcom = vhdl compile (vlog = verilog compile) vlib = create library vmap = map a library to a specified path  These are the 3 commands you end up using the most and should get you by in most situations.  You can find all of the arguments listed in the command reference manual for modelsim.  Modelsim requires you write a testbench for any design. This way you have far more control over the unit under test.

[Altera_Forum]

Hi, i think i have found the problem in another post, http://www.alteraforum.com/forum/showthread.php?t=33885&pp=10 (http://www.alteraforum.com/forum/showthread.php?t=33885&pp=10), what i didn't mention here yet (bad from my side) is that the top level code was done with schematics, so it seems that i need to convert it to vhdl