How to make some verilog codes invisible in a Quartus project?

[Altera_Forum]

I want to protect several critical and quite difficult-designed verilog code segments in a FPGA project, based on Quartus II 15.0 platform. Unfortunately, I don't know how to make them invisible in Quartus II. May I ask help in the forum since the codes are very important in the oncoming projects ? 

I'm looking forward for the reply ASAP. Thank you!

[Altera_Forum]

What exactly do you mean? Do you have code segments that you don't want to compile? Or are you trying to make the logic invisible?

[Altera_Forum]

Hi, 

 I guess you want to encrypt some verilog code so that it will not be visible to other users. For this you will have to find out if Quartus II has an encryption function using which you can encrypt the codes and deliver only the encrypted codes to others. The encryption should be such that it is readable by EDA tools other wise it would defeat the purpose.   There are lots of companies that do provide encrypted sources for designs, ones which we can compile but not see the code.

[Altera_Forum]

Thanks so much for the replies, and yes, I really want to encrypt some verilog code and make logic invisible in project.  

 How can I do those protecting works in Quartus II software then? Thank you again !

[Altera_Forum]

Well, Altera tools do not provide encryption/decryption functionality. The only way you can "hide" source code is to provide the other users with a netlist view of the modules that you wanna share. They can import and use these netlists in their designs. Have a look at the following link for more information. 

 https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10172006_472.html

[Altera_Forum]

You can create an encrypted bitstream programming file. Is that what you mean?