How to merge two or more buses?

[Altera_Forum]

I'm sorry for asking what it is probably a silly question, but i'm having trouble trying to merge 3 buses(2 buses containing 5 bits(0..4), 1 bus containing 16 bits(0..15) into one bus containing 26 bits. 

So, i'm not really sure what to do. To be more clear, this is how it looks like right now (and is not working. Error: (Can't find name for bus)) (Image attached). Basically, i want "shifter[0..26]" to have its first 16 bits coming from IMM bus. then, I would like to have "BusRT" into bits [16..20]. For last, BusRS being bits [21..25]. Can someone give me a hand in this? I got to solve this in order to be able to test my circuit.  Thanks.

[Altera_Forum]

Disconnect the busses and use named association to link them. 

 Label them shifter[0..15], shifter[16..20] and shifter[21..25] The fact they now have the same name will link them together when its compiled

[Altera_Forum]

--- Quote Start ---  Disconnect the busses and use named association to link them.  Label them shifter[0..15], shifter[16..20] and shifter[21..25] The fact they now have the same name will link them together when its compiled  --- Quote End ---     thanks Tricky, i got it! One more doubt, if i'm allowed to ask in this same topic.  I compiled my circuit and now i need to be able to check the values that are inside my registers during the execution. It seems that i can only check output pins and that may not be enough...

[Altera_Forum]

You could try using signaltap to check things in your design. 

But in the long run, you will be much better served using HDL (VHDL or Verilog) instead of schematics. They allow you to perform simulations, check code into version control and migrate your code to other vendors products.