Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to process this warning of PLL?

Altera_Forum
Honored Contributor II
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Hi Dears, 

 

In my design, i used PLL to generate pulses, which are less related with other clocks(come out from PLL). But when i generate by using PLL and get below critical warnings. Do i need to worry about them? 

 

 

 

Critical Warning (15537): Implemented PLL "mypll_calin:inst1|altpll:altpll_component|pll" as Enhanced PLL type, but with critical warnings 

Critical Warning (15526): PLL "mypll_calin:inst1|altpll:altpll_component|pll" has settings that may result in high compensation variability 

Info (15099): Implementing clock multiplication of 419, clock division of 2100, and phase shift of 0 degrees (0 ps) for mypll_calin:inst1|altpll:altpll_component|_clk0 port
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Altera_Forum
Honored Contributor II
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Can anybody help me about this issue?!

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