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How to recalibrate Stratix 10 E-tile cpri after CDR reference clock remaining stable ?

Vincent77
Beginner
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Hello!

Since the cpri's  CDR reference clock output by my clock chip is not generated as soon as it is powered on.As a result, the xcvr_reset_tx_done and xcvr_reset_rx_done cannot be pulled high, and the state_l1_synch cannot become an accurate value.I have to download the program twice to my device by JTAG to circumvent this problem. How to recalibrate Stratix 10 E-tile cpri after CDR reference clock remaining stable?

I have tried the following:

1) Configure according to the configuration process in PMA Calibration of the E-Tile Transceiver PHY User Guide(UG-20056 | 2021.12.09) . The PMA attribute code 0x0011 and 0x0001 have accurate return values,but didn't solve the problem.

2) To analog reset PMA when my clock chip output remains stable, but the problem is still.

 

Device: Stratix 10 ST110EN2F43E2

cpri IP : altera_cpri_ii 19.3.0

Quartus Prime Pro version : 20.4

 

Best regards,

Vincent

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