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Honored Contributor I

How to reduce the LE countes in my design ?

Dear Forum: 


I use the DE10-Lite with Max10 FPGA board to run the FLAC compressor encoder hardcore ; but happened fail as blow information ,  




error code: 

Info (171121): Fitter preparation operations ending: elapsed time is 00:07:47 

Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. 

Info (170189): Fitter placement preparation operations beginning 

Error (170011): Design contains 146846 blocks of type combinational node. However, the device contains only 49760 blocks. 

Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:47 

Info (11888): Total time spent on timing analysis during the Fitter is 8.08 seconds. 

Error (171000): Can't fit design in device 

Info (144001): Generated suppressed messages file D:/altera/Quartus/FLACPGA/fLaCPGA-master/fLaCPGA-master/HardwareEncoder/output_files/ 

Error: Quartus Prime Fitter was unsuccessful. 2 errors, 5 warnings 

Error: Peak virtual memory: 2608 megabytes 

Error: Processing ended: Mon Mar 27 22:32:48 2017 

Error: Elapsed time: 00:15:40 

Error: Total CPU time (on all processors): 00:15:54 






I know the LE counts already over Max10 LE limit(50K LE) , But I check up the FLaC Encoder spec , Which just use 22,706 ALMs in Stratix-V ; Might I know if 50K LE can Not cover 22.7K ALMs ? 

Why at Place and Fitting stage the Encoder LE upto 153,638 LE ? if ALM equals 7 times LEs ? 



If there any ways to optimize my design to reduce the LE counts within 50K ; or any parmaters setting error in my design ?  

it is most important for me now . 



In worse case ; if this encoder really need 153,638 LEs ; Is there any suggestion of FPGA product You can proposal to me ?, I also have another smaller function block need to burn into this FPGA. 



Thanks for all the help . 


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2 Replies
Honored Contributor I

If the design is too big, then you need to change the design, or change the FPGA. 

I cant really tell you what you need, as I have no idea what the project is or what the requirements are. That is your job to research...
Honored Contributor I

I would start by targeting a larger device so that the design will compile. Then you can look at fitter reports to see where the gates are being used and figure out if there's anything you can do about it. If the encoder is IP that you purchased then there's probably not much you can do. But if that's the case then the IP vendor should be able to give you guidance on which FPGA family and device you should target. If this is your own IP then it's all on you to find a fit.