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Hello guys,
I made an IP in verilog, and I wrote a .c file (converted in .hex) to test it. I simulated it with Quartus II using EDA Gate level simulation (In the EDA Gate level simulation option, there is a way to link a .hex file as a testbench). Now, I'm trying to do the next step, which is to implement the IP into the FPGA and run the .hex file. But I haven't found the way to link and run my .hex file. Does sb know how to do ? Best regards, JulienLink Copied
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