I do all my work in schematic/block design, and i made lot of "Lego" (bsf and bdf files) bricks for multiple sensors and communications with outside world. After compilation, i get like 500 warnings, and design works, but i want to make it more optimized so compiler would understand whats going on and maybe give less errors.
Is is possible to say that maximum frequency on that particular node will be lets say 50MHz ( like ADC reading core ) so when it is simulating timings, will not give me warnings and maybe do better job when optimizing?
You dont. You let the compiler compile your code. And then you supply timing specs to see if your code is capable of running at the specified clock frequency. If there are any issues then you can modify the code to improve timing by reducing the logic between registers etc.
For simulation, are you talking about simulating a post-compilation netlist? With good design practice (everything synchronous), good RTL simulation and the correct timing specs (in SDC file) you should be able to miss out the slow timing simulations and test directly on hardware.