How to simulate an inertial delay in ModelSim?

[Altera_Forum]

I am attempting to simulate an inertial delay in ModelSim. The code compiles in Quartus II; however, the delays in my code are not showing up in the simlation. I assume it is a configuration issue, but I have not found any tutorials on how to set Quartus and ModelSim up to account for intertial delays. The software is Quartus II 12.0 WE and ModelSim ASE 10d. 

 A simple case of what I'd like to simulate is:   A <= B or C after 5 ns;   During the simulation, the output A receives the "OR" of B and C, but the change is instant. There is no 5 ns delay.   Any How To's are appreciated.

[Altera_Forum]

--- Quote Start ---  I am attempting to simulate an inertial delay in ModelSim. The code compiles in Quartus II; however, the delays in my code are not showing up in the simlation. I assume it is a configuration issue, but I have not found any tutorials on how to set Quartus and ModelSim up to account for intertial delays. The software is Quartus II 12.0 WE and ModelSim ASE 10d.  A simple case of what I'd like to simulate is:   A <= B or C after 5 ns;   During the simulation, the output A receives the "OR" of B and C, but the change is instant. There is no 5 ns delay.   Any How To's are appreciated.  --- Quote End ---    Are you simulating in Quartus or Modelsim. Quartus will ignore "after" statement. Modelsim should not. There is no setting to enable or disable delay in modelsim as it is part of simulation modelling as far as I know. Check you are not overwriting your assignment. Also check your observation.

[Altera_Forum]

if you are interested how much time would it take for signal to go through (B or C) and then enter into register A, for this use "timing simulation" mode in modelsim. in this mode, modelsim thinks about logic gates that are inside altera and simulates results based on the real life delay information.  

if you just want to ignore real life transistor delays, and just want to test your logic,and artificially create a virtual delay, use functional simulation mode in modelsim. in this mode only your idea gets simulated. regardless of delays that would occur in real life. i never use this mode since it will not give realistic results, but, its fine for testing the logic of your circuit, and also simulating Artificial delays, in verilog for artificially delaying the action use# sign. for example: # 5 A <= B or C # means wait. 5 means wait for 5 times; and then execute the action. now question comes 5 -what? 5 nanoseconds? or 5 microseconds? or milliseconds? thats why you may need to add special command on top of verilog code, to tell the compiler what is the timescale nano micro or anything else. for this use: `timescale = 1ns/10ps 1ns means that you mean nanosecond timespace. and the one on picosecond side means simulation step. it will make resimulation step forward at each 10ps. use smaller number to get higher simulation detail. but it will increase  simulation time.  remember, the# 5 or whatever time,# 2# 9, this in real life does not exists. altera does not know what "Time" is. it's a machine. so don't count on using this kind of command in real life. if you want to delay a signal in real life, use LCELL. and delay time of LCELL will vary by temperature of processor itself. each LCELL may give you approximately 0.5ns delay. so if you need 5ns for example, you would actually need to pass signal through 10 LCELLs.but then if you get your device at winter cold place these delays will change by the laws of physics.

[Altera_Forum]

Hi everybody, I am trying to simulate delay introduced by LCELLs chains with timing simulation in ModelSim. 

I reduced the block to a DFF with output fed back to CLRN through a chain of LCELL. I output .vo file from QII, setting the Ignore LCELL buffers OFF. I include maxii library in the ModelSim project. Would you please have a quick look at the attached project? It might be I am missing something very basic and I do not see it :(  Thanks!

[Altera_Forum]

Have you checked the design to make sure it was as expected? Quartus may have optimised the design and removed some of the components you were expecting.  

Why are you trying to delay signals using LCELL though? using logic for delays is very unreliable.

[Altera_Forum]

I checked the design, screening all the Analysis and Synthesis settings..  

Is .sdo the file containing the delay right? So I thought but no matter how many LCELL I introduce, from simulation in ModelSim I always get the same glitch in output (not delayed) as you can see from attached screenshot. I am compiling and simulating the .vo file within ModelSIm, is that correct, does it link automatically to the .sdo? I am trying to simulate the delay introduced by LCELL chains in an already existing project, when I get a full understanding then I will be happy to consider more reliable solution, I guess with .sdc! Thanks a lot for attention!

[Altera_Forum]

Did you check the mapped design? are all the LCELLs present in the netlist as expected?

[Altera_Forum]

I had a better look at the .vo... indeed there is no NOT in the netlist.. mh 

I had selected OFF from "NOT Gate Push-Back" How come it does not implement a NOT? Thanks for your tips!

[Altera_Forum]

I meant check the netlist viewer - mapped design from the tools menu. Then you can see what the design has really mapped to on the hardware.

[Altera_Forum]

indeed NOT port is missing in the design. 

Do you have idea why QII not implementing it? I placed it! Thanks!

[Altera_Forum]

Quartus probably minimised your logic - check the synth warnings. 

You need to use attributes to tell quartus explicitly to not optimise your logic.

[Altera_Forum]

NOT port still not implemented and no warnings! this is puzzling me..  

 I did from settings>  "Remove redundant logic cells" , "off"  "Ignore LCELL buffers", "off" "PowerPlay optimization", "off"  How do I specify not to optimize the logic in block design file ?  Thanks!

[Altera_Forum]

0 error, 0 warnings 

but NOT gate is not implemented.. :cry: here attached the messages while executing. regards

[Altera_Forum]

Note gates are often implemented by inverting the input to a cell, so are basically "free". You will need to force an LCELL or some other logic.

[Altera_Forum]

I do not understand, do you mean I have to force the previous LCELL in the chain? 

In the attached screenshot, I have to force the output of LCELL inst11? How do I force the output, through the assignment editor? Thanks

[Altera_Forum]

I would say this is pretty telling: 

   --- Quote Start ---   Info (17016): Found the following redundant logic cells in design  Info (17048): Logic cell "inst4"  Info (17048): Logic cell "inst6"  Info (17048): Logic cell "inst7"  Info (17048): Logic cell "inst8"  Info (17048): Logic cell "inst11"  Info (17048): Logic cell "inst10"  Info (17048): Logic cell "inst9"  Info (17048): Logic cell "inst3"  Info (17048): Logic cell "inst4"  Info (17048): Logic cell "inst6"  Info (17048): Logic cell "inst7"  Info (17048): Logic cell "inst8"  Info (17048): Logic cell "inst11"  Info (17048): Logic cell "inst10"  Info (17048): Logic cell "inst9"  Info (17048): Logic cell "inst3"   --- Quote End ---    Because they are redundant, they will be removed during synthesis.

[Altera_Forum]

Hi Tricky, I did suppress optimization which is removing redundant cell, indeed on the Map Viewer all the LCELL are implemented - see screenshot. 

The problem is the NOT gate is not implemented.. how come? Maybe has to do with NOT inserted in a loop of LCELL? Hope to understand how to solve this!  Thanks a lot for your suggestions so far!

[Altera_Forum]

Hi all i was not able to solve the previous issue with simulating delay through a network of LCELL in Altera ModelSim. 

I am now using Program VWF tool from "New" as a simulation waveform editor to run functional simulation. I will update here when I find the way to simulate delays in the initial simple circuit with ModelSim