How to simulate schematic design?

[Altera_Forum]

The new version Quartus II has removed the vwf file, the simulation need to be done through third party tool like Modelsim. If I do a design through schematic design, how can I simulate it through Modelsim? As I know, Modelsim can only simulate HDL designs. 

 One approach seems to be using Quartus II to transfer schematic design to HDL design, then simulate the HDL in Modelsim, I just wonder whether there is other approach?  Thanks very much.

[Altera_Forum]

Conversion to HDL is the only choice if you want to simulate an RTL design. You can compile the design and create a post P&R netlist to simulate, but this is much slower. 

 The best option may be to forget about schematic altogether and just write the whole thing in HDL in the first place.

[Altera_Forum]

Got it, thanks very much!

[Altera_Forum]

This might be useful for you: 

 "I put together a little TCL script that automatically converts a schematic top-level entity to Verilog to help streamline preparation for ModelSim. "  http://www.alteraforum.com/forum/showthread.php?t=36262&highlight=tcl+macro+for+top-level+schematic+to+verilog+conversion

[Altera_Forum]

Thanks very much, czeh!

[Altera_Forum]

There is a program that you can create a waveform for your design like older versions of quartus.its name is "altera upds". you can simulate your schematics with it easily.

[Altera_Forum]

Thanks, where can I get it?

[Altera_Forum]

Another option is to stick with Quartus2 Version 9.1, unless you need the latest features. At least Version 9.1 runs with Win7 64 bits.

[Altera_Forum]

Yes, that is another approach. Thanks