How to synthesize quartus vqm or vo files

[Altera_Forum]

I have a design that I successfully implemented and synthesized on a Cyclone device, and would now like to port it to and asic flow. However, I don't want to re synthesize the original RTL verilog, but would rather try to synthesize the output of Quartus synthesis.  

The problem is that the vqm output generates a bunch of lcell primitives that my synthesis program does not recognize. I could not find a synthesizable definition of this primitive. Does it exist? Is there another flow that would work? Perhaps there is a synthesizable netlist that Quartus can dump before tech mapping that could work?  Thanks a lot in advance...

[Altera_Forum]

.vo files, for some reason I've never looked into, are not supposed to be synthesizable. VQM files can be, but only by Quartus. I've never heard of anyone writing libraries for other synthesis tools. Why would you want to do that? For starters, I'm guessing there are some legal issues(Quartus synthesis is free but I bet there's something stating it's results must target Altera devices). But it seems like you're adding another step that will be much more painful then targeting RTL, and open you up to technicaly issues(did I map this right, how do I functionally verify it, etc.). And of course the results will be big and slow, since the second synthesis tool won't have any high-level code to work with, just low-level gates.

[Altera_Forum]

--- Quote Start ---  I have a design that I successfully implemented and synthesized on a Cyclone device, and would now like to port it to and asic flow. However, I don't want to re synthesize the original RTL verilog, but would rather try to synthesize the output of Quartus synthesis.  The problem is that the vqm output generates a bunch of lcell primitives that my synthesis program does not recognize. I could not find a synthesizable definition of this primitive. Does it exist? Is there another flow that would work? Perhaps there is a synthesizable netlist that Quartus can dump before tech mapping that could work?  Thanks a lot in advance...  --- Quote End ---    Hi,  I don't think that will work at all. When Quartus implemements your design I sure it will use some hardmacros like DSP blocks , PLL's , Memories .... I'm quite sure that whether the vqm nor the vo- Files will be a "pure" netlist, which could be simply re-mapped to an ASIC library. You also should keep in mind, that the ASIC technology ist much faster then the FPGA's. As result you will get an ASIC with a larger size as necessary. The best results you will get by running a new synthesis with an ASIC synthesis tool.  Kind regards  GPK

[Altera_Forum]

VQM files are plain Verilog. If you insist, you can define the basic Altera primitives and synthesize them together. LE primitives should be fairly simply to define, others would be more difficult. 

 I don't see why you would want to do something like this, but it is doable.

[Altera_Forum]

target a Stratix and go HardCopy? :)