How to time constrain output pin connected to input pin on the same FPGA (design) ?

[Altera_Forum]

Hello, 

 My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay.   How do I constrain these ports to meet timing from SYNC_OUT to SYNC_IN? I don't know any setup or hold times as both ports are on the same FPGA.  Thaks in advance Vladimir

[Altera_Forum]

--- Quote Start ---  Hello,  My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay.   How do I constrain these ports to meet timing from SYNC_OUT to SYNC_IN? I don't know any setup or hold times as both ports are on the same FPGA.  Thaks in advance Vladimir  --- Quote End ---    You have three timing paths. input path, fpga path and output path. You set constraints for input path, and for output path. FPGA path (assuming it is between two registers) only needs clock definition and is checked by tool

[Altera_Forum]

Thanks for the reply. It is not the FPGA path I want to constrain. It is the output path through board delay and then input path on the same FPGA. 

 Maybe better question would be how to constrain synchronous signal between two FPGAs. It is clear how ho constrain FPGA output path to say external memory with known Tsu, Th, but how to constrain FPGA to other FPGA where Tsu and Th are not known (derived by the tool from input / output path constraints). Any ideas?

[Altera_Forum]

--- Quote Start ---  Thanks for the reply. It is not the FPGA path I want to constrain. It is the output path through board delay and then input path on the same FPGA.  Maybe better question would be how to constrain synchronous signal between two FPGAs. It is clear how ho constrain FPGA output path to say external memory with known Tsu, Th, but how to constrain FPGA to other FPGA where Tsu and Th are not known (derived by the tool from input / output path constraints). Any ideas?  --- Quote End ---    I see. One way is to put responsibility on one fpga and get the tCO (or tSU/tH) from its timequest datasheet) then apply that to other fpga. Though this may vary from build to build. Others put the responsibility shared between both but I don't see this any better.  edit. same applies for same one fpga, get tCO and apply input constraints accordingly.

[Altera_Forum]

just curious why wire out then in?

[Altera_Forum]

Yes, strange indeed. It's not wire out then back in, those are two chips running the same desing. FPGA-to-FPGA synchronization. Both FPGAs clocked from the same clock. But from timing point of view it is the same as it would be connected to itself.