Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to write a Verilog to implement -MULT(27x27) so that QPRO map the full functionality to 1 DSP?

DNguy11
Beginner
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Using QPRO it is possible to build an IP to implement -(X*Y) where X and Y are of 27 bit-width. However I find NO verilog writing style such that QPRO is able to map the full functionnality within 1 DSP

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Kenny_Tan
Moderator
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What device that you were using? You will first need to understand the architecture of the DSP. You can look into it in the resource property editor.

 

With that said, you can look into how to write the code in right click the verilog.v files -> insert template -> Verilog HDL -> Full Designs -> Arithmetic -> DSP features

 

Thanks

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DNguy11
Beginner
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Issue is with any stratix10 device. I already used the resource-property-editor to implement -(aXb) using the negate of the mult + the load_const of the DSP. So the solution is feasible. I already looked at the possible templates but nothing is proposed to implement -(A*B) within a single DSP

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Kenny_Tan
Moderator
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If that is the case, you might have to use the IP from the IP catalog. Can you look into using those?

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DNguy11
Beginner
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For portability reason I need to go though Verilog. Does it mean that QPRO is not able to infers such a basic DSP functionality?

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Kenny_Tan
Moderator
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That is correct, if you cannot find anything from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-design-recommendations-19-3.pdf?wapkw=12+recommended+hdl+coding+styles

 

Which means Qpro was not able to infer the DSP functionality base on your requirement. We can certainly make enhancement on this.

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