How to write a testbench which can initialize sub-module?

[Altera_Forum]

Hi all, 

 I need to simulate with the topmodule of my design. But i have to initialize the memory value in the memory sub-module. How can i do that in the testbench in for the top-module?  For example if the memory sub-module is named memory. And reg [17:0] ram[0:255] is defined in that module. To initialize the ram values, is it some thing like this?  initial begin memory.ram[0]=18'bXXXXXXXXX memory.ram[1]=18'bXXXXXXXXX ......  I tried, but it failed...

[Altera_Forum]

Here is my simple test code. 

    parameter MEM_SIZE = 1024;   reg [7:0] one_A[0:MEM_SIZE-1];    initial begin  for (int i=0; i<MEM_SIZE; i++)  one_A[i] = i + 10;  end

[Altera_Forum]

ertss,  

a module's internal variables are not accessible from other modules. Thus, you need to work around that.  You can either initialize the ram within the "memory" module itself or you can add some interface to the "memory" module that can write into the memory.

[Altera_Forum]

As rbugalho hinted, you need to "manually" write to the memory module to initialize it... For example, if you want to initialize it to all std_logic '0's, you need to *write* to the memory the value of '0' at every clock cycle. 

 Altera's devices (and probably other FPGA vendors too) doesn't support asynchronous clearing/resetting of memory contents, probably because it is too expensive to implement on silicon.

[Altera_Forum]

I don't understand some of the statements. 

   --- Quote Start ---  For example, if you want to initialize it to all std_logic '0's, you need to *write* to the memory the value of '0' at every clock cycle.  --- Quote End ---   But the original question is referring to an initial block, which is simply inferring a constant initialization of a RAM, similar to a *.mif file. Furthermore, the discussion is about simulation rather than synthesis. In simulation, "everything goes".    --- Quote Start ---  a module's internal variables are not accessible from other modules  --- Quote End ---   Generally, Verilog allows access through hierachical names. So the question is, why it's not working here.