How would you create infinite simulation loop in modelsim using erilog/ vhdl

[Altera_Forum]

Any ideas, hints would be helpful.

[Altera_Forum]

You could just post your homework assignment for us. :) 

 You could create a task that contains your loop. Then just schedule the task to run at some predefined interval.  Jake

[Altera_Forum]

Hi Jakob, 

 I wish this was only an assignment :)    I do thank you though and if you do have any other suggestions please do let me know.    thanks

[Altera_Forum]

I presume you are aware of the $stop and $finish directives in verilog? 

 Descriptions from the sutherland HDL reference: $finish;  Finishes a simulation and exits the simulation process. $stop;  Halts a simulation and enters an interactive debug mode.  Jake

[Altera_Forum]

thanks for your help..

[Altera_Forum]

This should make modelsim get stuck in an infinite loop in VHDL: 

  signal a : std_logic := '1'; signal b : std_logic := '0'; ... b <= a and not b;

[Altera_Forum]

thanks tricky... did end up doing something like that. general question can anyone give me an example how do i make 2 always loops to be continuously switching between each other

[Altera_Forum]

you can try  

... process  begin  ......  loop  wait until clk='1';  ......  end loop; end process;

[Altera_Forum]

Did I conceive a circuit under quartusII and do I want validated it by a file of data to elaborate by a program in C language, and to recover the exits as a file text, how to make?