I think it is related to having multiple plls that I am reconfiguring. If I turn off the feature for one of the plls then I don't get the error anymore.
The above error can causes by multiple reasons. May be there is an PLL and LVDS transmitter combination is not working properly in Quartus 12.1. So requesting to try on the latest version of Quartus.
Thanks for your reply. I am targeting a stratix 3 device so I believe I am stuck with an older version. One of the PLLs is indeed used for 3 ALTLVDS_TX blocks. Does that put some restrictions on which plls or the number of plls that can be used with the ALTPLL_RECONFIG function?
If the device is Stratix 3, try to use Quartus 13.1 Version.
For your below question
Does that put some restrictions on which plls or the number of plls that can be used with the ALTPLL_RECONFIG function?
In my opinion, there will not be any issue. These are the guidelines Page no:52 for the PLL usage.
I tried Quartus 13.1 and this also did not work.
I did figure out a solution to my problem. The problem seemed to be related to global clock resource utilization around the PLLs. The clock input for all 3 of the ALTPLL_RECONFIG blocks (I believe this ends up feeding the pll_scanclk also) in my design was originally sourced from the same global clock net. I changed this so that each clock was generated locally by logic and forced the tool to prevent the use of global routing on the clocks feeding each reconfig block. This change allowed my design to compile and everything is working fine.