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CHatz
Novice
1,340 Views

I am using Intel IP components. I used quartus to create the ModelSim script to compile the design. When ModelSim attempts to start simulation, I get Errors for all the Intel IP as shown in the details section.

# ** Error: (vsim-3935) C:/Projects/A10_BSM/BSM_EPL_PCL_EGL/simulation/modelsim/../../new_ip/CCP_RAM/sim/CCP_RAM.vhd(45): Port 'A_IN' not found in the connected module.

#  Time: 0 ps Iteration: 0 Instance: /bsm_epl_pcl_egl_bsf_tst/uut/b2v_inst45/b2v_inst3/b2v_inst136/ram_1port_0 File: C:/Projects/A10_BSM/BSM_EPL_PCL_EGL/simulation/modelsim/../../new_ip/CCP_RAM/ram_1port_180/sim/CCP_RAM_ram_1port_180_iletabi.v

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3 Replies
AnandRaj_S_Intel
Employee
41 Views

Hi,

 

Can you share more information On IP used & its Configuration, Quartus and modelsim tools version used in your design process?

Are you trying to simulate single IP or complete design?

Share transcript of modelsim.

 

Make sure appropriate version of Quartus tools and modelsim are used.

Example if you use Quartus 18.0 you need to use modelsim 10.6c if Quartus 17.0 use modelsim 10.5b.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

CHatz
Novice
41 Views

Hello Anand,

 

I am using the Quartus 18.0 package. This package came with the ModelSim 10.5b version and that's the version I am using to

simulate.

 

 

I am simulating a complete design containing Intel IP and custom components.

Unfortunately, the Intel Web Site won't allow me to upload the files.

 

 

 

 

 

 

 

Costas Hatzinikolaou,

 

Sperry Rail Corporation.

CHatz
Novice
41 Views

Adding the libraries in the top level file, eliminates the Errors:

--edits for simulation

library altera_mf;

use altera_mf.all;

library altera;

use altera.all;

 

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