IO Assignment Analysis performance

[Altera_Forum]

The IO Assignment Analysis step is taking hours of run time. Given that all it has to do is match up my IO assignments with the device pins, I would expect it to take seconds. 

 Has anyone else had this problem and come up with a way to fix it?

[Altera_Forum]

Maybe we can help if you give us some more information. 

What version of Quartus are you using? Which device are aiming at? How many IO do you use?  Regards, Ton

[Altera_Forum]

--- Quote Start ---  Maybe we can help if you give us some more information. What version of Quartus are you using? Which device are aiming at? How many IO do you use?  Regards, Ton  --- Quote End ---    +-----------------------------------------------------------------------------------+ ; Flow Summary ; +-----------------------------------+-----------------------------------------------+ ; Flow Status ; Successful - Thu Jun 17 06:46:48 2010 ; ; Quartus II 64-Bit Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Full Version ; ; Revision Name ; ttttt ; ; Top-level Entity Name ; tttttt ; ; Family ; Stratix IV ; ; Device ; EP4SE530F43C3ES ; ; Timing Models ; Final ; ; Met timing requirements ; N/A ; ; Logic utilization ; 59 % ; ; Combinational ALUTs ; 178,642 / 424,960 ( 42 % ) ; ; Memory ALUTs ; 392 / 212,480 ( < 1 % ) ; ; Dedicated logic registers ; 128,179 / 424,960 ( 30 % ) ; ; Total registers ; 128179 ; ; Total pins ; 434 / 976 ( 44 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 974,508 / 21,233,664 ( 5 % ) ; ; DSP block 18-bit elements ; 491 / 1,024 ( 48 % ) ; ; Total GXB Receiver Channel PCS ; 0 ; ; Total GXB Receiver Channel PMA ; 0 ; ; Total GXB Transmitter Channel PCS ; 0 ; ; Total GXB Transmitter Channel PMA ; 0 ; ; Total PLLs ; 1 / 12 ( 8 % ) ; ; Total DLLs ; 0 / 4 ( 0 % ) ; +-----------------------------------+-----------------------------------------------+  +-------------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +---------------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------------+--------------+--------+----+-------------+ ; Analysis & Synthesis ; 01:33:09 ; 1.0 ; -- ; 01:32:23 ; ; I/O Assignment Analysis ; 01:56:57 ; 1.0 ; -- ; 01:56:50 ; ; Fitter ; 02:47:25 ; 1.7 ; -- ; 03:12:45 ; ; TimeQuest Timing Analyzer ; 00:06:45 ; 2.1 ; -- ; 00:08:59 ; ; Assembler ; 00:03:21 ; 1.0 ; -- ; 00:03:19 ; ; Total ; 06:24:16 ; -- ; -- ; 06:50:57 ; +---------------------------------+--------------+--------+-----+------------+

[Altera_Forum]

Of my 6.5 hour build time, 2 hours are consumed doing "I/O Assignment Analysis".  

 All of my used pins are assigned locations.   Is this just a subset of fitting. Can I just disable it?

[Altera_Forum]

Apparently, I can just disable "I/O Assignment Analysis" under setting and reduce my compile time from 6.5 hours to 4.5. 

 I guess the intent of this "feature" it to give me "I/O analysis" an hour earlier than I would ordinary get is at the cost of making my overall run 2 hours longer. I guess this could have been a good idea the first time I ran it.