Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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IO open drain configuration question.

adamShiau
Novice
942 Views

Hi,

I read in the Cyclone IV device handbook that I/O pins can be configured in open-drain mode.

However, I couldn't find the chapter that explains how to set this up.

I tried using the Pin Planner in Quartus IDE, but I couldn't find an option to configure open-drain mode there.

Could you guide me to an example or instructions for setting this up?

Thank you!

 

Adam Shiau

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FvM
Honored Contributor II
820 Views

Hi,

you don't need assignment pin planner or assignment editor to implement open drain, you can also infer open drain output directly in HDL by driving an inout pin to '0' and 'Z' respectively. Resource Property Editor shows that open drain mode is implemented for output buffer.

SDA <= '0' WHEN sda_oen = '0' else 'Z';

Default compiler setting AUTO_OPEN_DRAIN_PINS on is presumed.

Regards

Frank

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AqidAyman_Intel
Employee
837 Views

Hello Adam,


Have you been able to look at the Assignment Editor?

You open the Assignment Editor by clicking Assignments > Assignment Editor.

The Assignment Editor allows you to view, create, and edit assignments.


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FvM
Honored Contributor II
821 Views

Hi,

you don't need assignment pin planner or assignment editor to implement open drain, you can also infer open drain output directly in HDL by driving an inout pin to '0' and 'Z' respectively. Resource Property Editor shows that open drain mode is implemented for output buffer.

SDA <= '0' WHEN sda_oen = '0' else 'Z';

Default compiler setting AUTO_OPEN_DRAIN_PINS on is presumed.

Regards

Frank

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AqidAyman_Intel
Employee
590 Views

Thank you, Frank, for your valuable input.


Hi Adam,


I wish to follow up, do you need more support on this matter?


Regards,

Aqid


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