Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

IO pin definition and TCL file

Altera_Forum
Honored Contributor II
‎04-20-2010 09:22 AM
1,210 Views

I am doing a project on a MAXII EPM570T144C5. 

 

When I do "Project | Generate Tcl file for project..." one of the assignments comes up 

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 

 

but it isn't a STRATIX device. If I import the Tcl file back into the system to regenerate the project, it gives me a warning message that it is over-riding Stratix as the device is MaxII. 

 

Any suggestions how to fix things?
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎04-20-2010 04:43 PM
515 Views

what version of software are you using? can you paste the warning here? i tried a simple test case and didn't see any warnings about Stratix.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎04-21-2010 08:06 AM
515 Views

TO_BE_DONE

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.