[ISSP] In-System Source and Probe -> How to insert to RTL?

[amildm]

Hello, 

I'm using Quartus v19.3.

How is it possible to insert the ISSP to RTL? 

How to define several ISSP's - each one synchronous to its driving clock??

Should I add synchronous stages to ISSP? How?

Should ISSP be based on the Signal Tap signals? Cannot I define different signals for ISSP and SignalTap?

Thanks!

[ShengN_Intel · Accepted solution]

Hi,

How is it possible to insert the ISSP to RTL? 

In IP catalog, choose the ISSP IP, specify the source/probe parameters and enable Use Source Clock. After generating ip, use the instantiation template from _inst.v or _inst.vhd in ip generated folder to your top module.

How to define several ISSP's - each one synchronous to its driving clock??

You can use multiple ISSP IP and declare multiple instances in top module. By enabling Use Source Clock, you can associate each synchronous to its driving clock respectively.

Should I add synchronous stages to ISSP? How?

Probably not need. Regardless single clock domain or multiple clock domains, the tool will automatically handle the synchronization of signals based on the specified clock domains during the insertion process.

Should ISSP be based on the Signal Tap signals? Cannot I define different signals for ISSP and SignalTap?

You can define different signals for ISSP and SignalTap. While inserting ISSP, you can choose the signals you want to monitor, and they don't have to be the same as the ones you use in SignalTap.

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi

Let me know if you have any further update, concern or follow-up on the previous post sent?

Thanks,

Best Regards,

Sheng

[amildm]

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