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Altera_Forum
Honored Contributor I
1,327 Views

If loop with parameters.

I have this bothering me for quite some time now. I make a simple loop with ifs to create a state machine, where I just want stuff to happen in a certain order after some flags are activated.  

 

Something like this: 

 

reg state; parameter stt_idle = 2'b00; parameter stt_one = 2'b01; parameter stt_two = 2'b10; parameter stt_three = 2'b11; initial state = stt_idle; always @ (posedge clk or negedge reset) begin if(!reset) state<=stt_idle; else begin if(state==stt_idle) begin if(...) state<=stt_one; else state<=stt_idle; end else if(state==stt_one) begin if(...) state<=stt_two; else state<=stt_one; end else if(state==stt_two) begin if(...) state<=stt_three; else state<=stt_two; end else if(state==stt_three) begin if(...) state<=stt_idle; else state<=stt_three; end end end  

 

I'm spying the signals in signal tape and for some reason, sometimes something happen where all the state.stt_... signals are all at 0 making the state machine going out of the loop and my design breaks. I tried to use a buffer state where I add an else at the end and do state=buf_state. That makes it so the signals go back to the loop, however this wall make me lose some state transitions, since this break seems to happen whenever there is a state change. For example, imagine my code was in the idle state and it was suppose to go to the one state however. It broke and it goes back to the idle, because it never entered the one state. 

 

Has anyone ever encounter that problem? How did you solve it? 

Do you see a flaw in the code that could be a cause for this? 

Anyway you can help me? 

 

Thanks, 

Ricardo
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4 Replies
Altera_Forum
Honored Contributor I
30 Views

In your actual code, are you using blocking or non-blocking assignments for the state transition assignments?

Altera_Forum
Honored Contributor I
30 Views

Although I didn't use it in the code block, I use "<=" to execute the code in parallel. Will modify that in the example to make it clear. Sorry for the misunderstanding.

Altera_Forum
Honored Contributor I
30 Views

Have you tried using case statements instead of ifs? I can't see anything wrong with the way you've written the ifs but what you're describing would work equally well (if not better) with a case statement so it'd be worth seeing if the compiler behaves better with that...

ricardoluz
Beginner
30 Views

(I am the author of this question)

 

I think I first used case instead of ifs, and then started using ifs because of this exact problem but got the exact same issue.

 

I'm using a 320 MHz PLL in this module (the fastest clock I use in my design) but I fill all timing requirements in time quest.

 

Do you think that might influence it anyway?

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