Import Package error System Verilog

[JNika]

Hello,

I have a few packages that I have written like this:

package A;

-- 

--

endpackage

package B;

import A::*

---

-- 

endpackage

package C;

import A::*;

import B::*;

endpackage

In the file using package C, the error I am getting is as follows:

Error (10864): SystemVerilog error at C.sv(26): TMP was imported from multiple packages with ::* - none of the imported declarations are visible.

Is this problem because I am importing A::* in both package A and package C?

Any help to rsolve this is greatly appreciated.

Thanks in Advance~

--

Nikhil Pratap

[Vicky1]

Hi,

"Is this problem because I am importing A::* in both package A and package C?"

Yes, Please refer the below attached doc from Language reference manual(LRM) especially

"Table 26-1—Scoping rules for package importation" & Examples under the "26.6 Exporting imported names from packages"

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[dave_59]

It would help if you showed the places where TMP was declared and referenced. The import A::* by itself is not the problem. Most likely because you have declared TMP in both packages A and B and tried to reference it in C.