Importing Synplify Pro Netlist to Quartus II for P&R

[Altera_Forum]

Hi, 

I am trying to get better timing result after porting the netlist created by Synplify Pro to Quartus(Stratix IV device). If i invoke quartus through Synplify Pro , It is importing two files(.vqm and .scf file) Here are some of the queries i have: 1) While i am running quartus individually and importing vqm and scf file, its giving error as "top entity name *" does not exit, although the same thing is working if i invoke the quartus through synplify_pro 2) After synthesis in Synplify Pro I am getting 131.5 Mhz and the critical path contains a block whose routing delay is around 65% and logic delay 35%, so i expected that after P&R the timing performence would improve, but The fmax summery from Quartus is giving only 68Mhz which is highly discouraging. 3) One more thing i am selecting device as " EP4SE820H40C3 in Stratix IV" , while running Fitting and Timing Its giving Warning "Warning: Timing characteristics of device EP4SE820H40C3 are preliminary" , Is it a valid warning and if so how to solve this. 4) As i am generating the netlist from synplify pro, Why to run Synthesis and Elaboration again in Quartus, As if i try to run fitter directly on the imported netlist and scf, its giving error that analysis and synthesis needs to run before fitting. So is my setup wrong.  If anyone of you have any idea please let me know the issue.

[Altera_Forum]

1) Is the error from an assignment or something? Why does it think there's an entity called *? (If the top-level entity is wrong in Quartus, found in Assignments -> Settings -> General, then it wouldn't go through at all and there would be nothing to do timing analysis on) 

2) Why would place-and-route make it faster. 65% routing is a decent estimate. Of course everything is just an estimate. I wouldn't rely on Fmax summary. Besides not being a complete picture(Fmax is only valid if your source and destination clocks are the same, so all cross clock paths are ignored), you can't get detailed analysis. Assuming you have .sdc constraints, launch TimeQuest and run Report All Summaries from the left Task Window(near the bottom). Then go to the Setup Summary report and see the worst domain. Right click on that and Report Timing. From that dialogue box you can get detailed reports on paths and can analyze what's going on. 3) The device's timing models are not final. That will occur in a future version of Quartus based on silicon characterization(that's a pretty new device and I'd make sure you can get some). In general, when they become final you won't even notice, but no guarantees. 4) Synthesis still runs on a .vqm, it's just really fast since there's not a lot for it to do. But it still needs to take that .vqm and translate it into the device to be fit. (And if you turn on Assignments -> Settings -> Analysis & Synthesis -> WYSIWYG Resynthesis, then Quartus will actually break up the .vqm into equations and resynthesize. This generally gives better results.