Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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In-System Source and Probes Usage

Altera_Forum
Honored Contributor II
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Hi, 

 

I am designing a system in which i need to program external SPI interface memory from JTAG. I am using MAX II EPM240 Device. I have made the SPI Master program and also tested it. The SPI Memory is of 4 Mbits. I want to write the data to SPI interface memory using JTAG. Is it possible to write the data into the memory using in-system source and probes component of Quartus II? Does any one have any idea about using In-System Sources and Probes? I have read the user guide for it. From it i conclude that it is only used for the debugging purpose.  

 

Please help me.. 

 

Regards, 

Jigar G. Shah
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Altera_Forum
Honored Contributor II
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You can use it for any purpose that fits your application. I've used it (together with In-System Memory Editor) for calibration and test. Unfortunately, there's no documented API in the Altera JTAG stack for Source&Probe and other virtual JTAG functions. So Source&Probe capabilities practically depend on the effort your willing to spend to understand the interface.  

 

The topic, also possible interface to user applications has been discussed in the forum before. 

 

Another usual method to program memory connected to JTAG capable devices is by generic boundary scan access to the CPLD/FPGA pins, although it's rather slow.
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Altera_Forum
Honored Contributor II
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Can you guide me how i can use it to program the external memory. Do u have any idea? 

 

Thanks and Regards, 

Jigar G. Shah
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Altera_Forum
Honored Contributor II
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In my application, I have a Source&Probe parallel interface (address, data, r/w and manual override of regular function) to the respective components in the production design. But it's an FPGA, where a few ten multplexers and registers don't count. I see a problem with short resources in EPM240.  

 

If not needed repeatedly, a different configuration could be programmed to the MAX II for initial memory programming. 

 

The lowest resource count and most effective operation could be achieved with a Virtual JTAG function similar to SFL (serial flash loader), that streams multiple JTAG bits in one shift action directly to the memory. SFL is not enabled for MAX II by the Megawizard, but the sources are present in the library folder. 

 

I still think, that the said generic boundary scan method is most simple to implement, cause it doesn't depend on undocumented Altera interfaces. Commercial and public domain tools should be available.
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Altera_Forum
Honored Contributor II
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Thanks, 

 

i have read about the boundary scan documents earlier, it seems that it do not support MAX II family. 

 

Regards, 

Jigar G. Shah
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Altera_Forum
Honored Contributor II
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Which document? There are BSDL files for any JTAG capable device, also for MAX II.

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Altera_Forum
Honored Contributor II
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sorry for late reply. I was out of station. Please find the attachment in which it shows that the MAX II does not support boundary scan JTAG.

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Altera_Forum
Honored Contributor II
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You may want to refer to the recent Altera documents rather than an Application Note that was apparently written before MAX II production start. The said document also don't mention Cylone II, Cyclone III etc. Do you conclude, they have no boundary scan function.  

The MAX II BSDL files can be found at altera.com, as previously said. 

http://www.altera.com/support/devices/bsdl/max2/max2-index.jsp
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Altera_Forum
Honored Contributor II
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Thanks for info. I will check out the link. Thanks.

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Altera_Forum
Honored Contributor II
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Hi all, 

I am a novice to using Quartus II tool and i have been given an assignment to learn and work on the board about "Design Debugging Using In-System Sources and Probes". 

I am not getting how i am to begin with.:confused: 

could anyone help me in this aspect
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