In-system memory content editor cannot read/write to RAM

Altera_Forum · ‎03-14-2016

The In-system memory content editor cannot read or write a RAM that was instantiate for the IP core library.

The RAM (altsyncram) concerns a single port configuration. Read and write commands from other (own) blocks is going well, but the content editor gives a depth of 0 addresses of the RAM.

I have already added the default parameter: CYCLONEIV_SAFE_WRITE RESTRUCTURE, but it didn't work out anything.

In the RTL and technology viewer, the RAM block is connected to the JTAG logic.

Used soft- and hardware:

Quartus II Version 14.1.0 Build 186 12/03/2014 SJ web edition

DE0-nano / FPGA: EP4CE22F17C6

VHDL code:

altsyncram_component : altsyncram
    GENERIC MAP (
        clock_enable_input_a => "BYPASS",
        clock_enable_output_a => "BYPASS",
        intended_device_family => "Cyclone IV E",
        lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM",
        lpm_type => "altsyncram",
        numwords_a => 32,
        operation_mode => "SINGLE_PORT",
        outdata_aclr_a => "NONE",
        outdata_reg_a => "UNREGISTERED",
        power_up_uninitialized => "FALSE",
        read_during_write_mode_port_a => "DONT_CARE",
        widthad_a => 5,
        width_a => 8,
        width_byteena_a => 1
    )
    PORT MAP (
        address_a => address,
        clock0 => clock,
        data_a => data,
        wren_a => wren,
        q_a => sub_wire0
    );

Anyone an idea why I cannot read/write with the in-system memory content editor?

Thank you in advance,

Rutger

Altera_Forum · ‎03-14-2016

Do you have a jtag Avalon master connected to what you are trying to modify?

Altera_Forum · ‎03-15-2016

Yes I have, the In-system memory content editor can scan the JTAG chain with the USB-blaster. The DE0-nano is connected with the USB cable to my PC.

When i instantiate some LPM constants, I can proper read and write these constants with the content editor.

The problem is not the connection (I thing) but the In-system memory content editor says that the dept of the RAM is 0 (should be 2^5, see code above).

Altera_Forum · ‎03-15-2016

Usually I would use Qsys onchip-memory to instantiate my altsyncram with in-system memory editor turned on.

Anyway, can you try changing the instance name to something unique? ie

lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=RAM_101_INSYSTEM",

Altera_Forum · ‎03-15-2016

I have tried it, but the result is the same.

Altera_Forum · ‎03-15-2016

Could you check whether did Quartus optimize your RAM to be MLAB? Sometimes because your memory is too small and able to fit into a MLAB, quartus will convert it for you.

Can you humor me by setting the ram block type? ie

ram_block_type => "AUTO", or ram_block_type => "M9K",

Altera_Forum · ‎03-15-2016

I have tried both, but it didn't work out.

The MLAB configuration is not supported by the Cyclone IV FPGA.

When type is set to auto, the M9K is also instantiated.