Include .qsys Qsys systems to VHDL Quartus project

[Altera_Forum]

Hi all, 

 I have some systems designed in Qsys and would like to add them to my Quartus project. So here is what I did: 

• Design systems in Qsys  
• Include .qsys files to the Quartus project  
• Reference them with "library system;" and use them with "ip : entity system.system" with "system" being the Qsys system  
• Compile the Quartus project  

  But I get an error: Error (10481): VHDL Use Clause error at system_wrapper.vhd(56): design library "system" does not contain primary unit "system".  I correctly see the library "system" and the IP files in Design Units and the top "system" file is in Verilog. My project is in VHDL and I believe this is why Quartus do not find the system. I also would like to mention that everything works fine when generating the Qsys system manually in VHDL and including the .qip file.  How could I get around the error when including the .qsys file? (easier for project management)

[Altera_Forum]

Use "work" in stead of "system". It is default so you can do without the 'library' clause -> "ip: entity work.system"

[Altera_Forum]

Hi josyb, 

 This doesn't work since the system "system" is under the library "system" once the .qsys file included. When including the .qip file, I use "ip: entity system.system" and it works fine.

[Altera_Forum]

Right. I should have thought a bit longer about that. Altera used to ignore the 'library' other than 'work' at that time, several years back and I just adapted. But you remind me now that indeed specifying the Qsys generated component by using "ip: entity.work.system" doesn't work either ... and I then just copied the example HDL component over ... 

Thanks for the tip.  Regards, Josy

[Altera_Forum]

--- Quote Start ---   I have some systems designed in Qsys and would like to add them to my Quartus project.   --- Quote End ---    You have several options with Qsys;  1. Include the .qsys file into the project and Quartus will build it.  2. Include the .qip file into the Quartus project, and you have to build the .qsys file  I'm a "control freak", so I went with option 2 :)  This allows me to use ip-generate in scripts to generate the synthesis model and/or the simulation model.  The arguments to ip-generate can be copied from the Qsys console as its processing the design (after you click the "generate" button).  The BeMicro-CV DDR example in this thread has a synthesis script that uses this approach (scroll down to post# 5).  http://www.alteraforum.com/forum/showthread.php?t=43992  The downside of .qsys files is that they are Quartus version-specific, and not easily scriptable, since they are written in XML. However, the AlteraWiki has a nice solution;  http://www.alterawiki.com/wiki/qsys_scripts  you can use this to convert the XML to Tcl. The Tcl script can then have Quartus-version dependent logic (eg., adds/removes ports or generics). So your synthesis script can convert the Tcl back to Quartus-version specific XML, then run that through ip-generate, and you have a nice portable solution that you can check into your favorite code-versioning repo, but yet use with multiple Quartus versions.  Cheers, Dave

[Altera_Forum]

Dave, 

 I had a look at the project but if I get it correctly, it is not what I would like to do.  I would like to use option 1 (include .qsys file into the project) and have Quartus build it to be able to include it from a VHDL file. Right now, it seems to generate the Qsys system top IP in Verilog no matter what and there is no option to ask for VHDL.  I use .qip file generated by Qsys at the moment and asks Qsys to generate the top IP in VHDL. However, I would like to move to .qsys file to be able to directly go into the system in Qsys from Quartus and for ease of use. My goal here is to avoid any manual steps such as generating the Qsys system from Qsys (needed right now) or modifying a TCL script.  Regards, Mohamed

[Altera_Forum]

Hi Mohamed, 

  --- Quote Start ---   I would like to use option 1 (include .qsys file into the project) and have Quartus build it to be able to include it from a VHDL file. Right now, it seems to generate the Qsys system top IP in Verilog no matter what and there is no option to ask for VHDL.   --- Quote End ---   I haven't found any way to control the build via including .qsys directly, which is why I went with Tcl scripting.  Practically though, why do you care if its VHDL? So long as the design synthesizes, you shouldn't really need to care.    --- Quote Start ---   I use .qip file generated by Qsys at the moment and asks Qsys to generate the top IP in VHDL. However, I would like to move to .qsys file to be able to directly go into the system in Qsys from Quartus and for ease of use. My goal here is to avoid any manual steps such as generating the Qsys system from Qsys (needed right now) or modifying a TCL script.   --- Quote End ---   There are no manual steps with the Tcl script. The script automates everything.  In the case of the DDR controller, it also automates the application of the DDR pin constraints file generated by the IP core via a post-flow script. None of the Altera examples do this :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi Mohamed,  I haven't found any way to control the build via including .qsys directly, which is why I went with Tcl scripting.  Practically though, why do you care if its VHDL? So long as the design synthesizes, you shouldn't really need to care.   There are no manual steps with the Tcl script. The script automates everything.  In the case of the DDR controller, it also automates the application of the DDR pin constraints file generated by the IP core via a post-flow script. None of the Altera examples do this :)  Cheers, Dave  --- Quote End ---     Hi Dave,  I was using SOPC builder previously and have just now learned how to use Qsys... So I came across your post where you mentioned "Practically though, why do you care if its VHDL? So long as the design synthesizes, you shouldn't really need to care."   I have a project consisting of several blocks in schematic interface, they are mainly custom blocks written in VHDL, what I want to do is, to include the Nios system in the schematic interface.   In SOPC, when I was trying to generate the Nios system, I will be prompted to select either Verilog or VHDL whenever I want to create a new Nios system, but I could not find this option in Qsys.  May I ask:  1. Is there a way to select either Verilog or VHDL to be generated in Qsys? 2. Does it matter? If no, could I still combine the Nios system generated in Verilog to communicate well with all the custom blocks written in VHDl where I am going to combine all of them in schematic file?  Thank you in advance for your guidance

[Altera_Forum]

--- Quote Start ---   I have a project consisting of several blocks in schematic interface, they are mainly custom blocks written in VHDL, what I want to do is, to include the Nios system in the schematic interface.   --- Quote End ---   So you have VHDL that you have connected together using a schematic?  Depending on how much work it would take, I would recommend modifying your VHDL so that each component has an Avalon-MM interface. Of course that depends on what your VHDL does, so if you can describe your existing components, I could recommend a solution.    --- Quote Start ---   In SOPC, when I was trying to generate the Nios system, I will be prompted to select either Verilog or VHDL whenever I want to create a new Nios system, but I could not find this option in Qsys.   --- Quote End ---   Under the "Generate" tab or menu option (depending on Qsys version), you can select Verilog or VHDL for simulation, or on the newest version for synthesis. On older versions of the tools, synthesis only produced Verilog code. This was not really an issue, as even if you instantiated the Qsys system into a top-level VHDL file, all you had to do is add a component declaration.    --- Quote Start ---   could I still combine the Nios system generated in Verilog to communicate well with all the custom blocks written in VHDl where I am going to combine all of them in schematic file?   --- Quote End ---   Yes, its no problem mixing Verilog, VHDL, and schematics. However, any serious developer should also be simulating their code in Modelsim. While it is possible to generate an HDL version of a schematic, I would recommend moving over to an entirely HDL development flow. Modelsim-SE can be used to simulate mixed Verilog and VHDL designs. If your NIOS II system is the only part of your design that is Verilog, then you can generate its simulation in VHDL, and have a 100% VHDL design that you can simulate in Modelsim-ASE.  Cheers, Dave