Including Files in Verilog

[Altera_Forum]

I am a noob at Quartus. I have a large chunk of a very large ASIC design that I want to implement in an FPGA. The design to be implemented is spread across several directories. 

 I cannot get Quartus to recognize any of the verilog include files. The .vh files are in the same directory as the files that call them. I tried    set_global_assignment -name SEARCH_PATH "full path"   in the .tcl file, but it has no effect.   Any advice?   Thanks.

[Altera_Forum]

--- Quote Start ---   Any advice?    --- Quote End ---  Use Tcl to create the absolute path name of the file, and then use that in the Quartus assignment:  set_global_assignment -name VERILOG_FILE $full_path_to_file  Given the top-level directories where your ASIC source is located, you can use Tcl glob to automate listing of all the Verilog files.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Use Tcl to create the absolute path name of the file, and then use that in the Quartus assignment:   set_global_assignment -name VERILOG_FILE $full_path_to_file   Given the top-level directories where your ASIC source is located, you can use Tcl glob to automate listing of all the Verilog files.   Cheers, Dave  --- Quote End ---     Ok, I did say I was a noob. What is the tcl command to get the absolute path name? BTW I already tried adding these files to the compile list in Quartus. It didn't change anything.   Mike

[Altera_Forum]

I tried: 

 set my_path file join root_of_path tail_of_path set_global_assignment -name VERILOG_FILE $my_path   This has no effect. I tried it with just the path, and with the file name.   Mike

[Altera_Forum]

Hi Mike, 

  --- Quote Start ---   I tried:   set my_path file join root_of_path tail_of_path set_global_assignment -name VERILOG_FILE $my_path   This has no effect. I tried it with just the path, and with the file name.    --- Quote End ---  There's examples of how to script Quartus in this tutorial:  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  If you look at one of the synthesis scripts, eg.,  altera_jtag_to_avalon_mm_tutorial\hdl\boards\bemicro_sdk\qsys_system\scripts\synth.tcl  you'll see an example of how the script determines the path to the tutorial source, and then uses absolute paths in the subsequent assignments.  Cheers, Dave