Incorrect Latch Edge in Timequest

[Altera_Forum]

I have a design which uses a PLL that introduces a phase shift of 625ps between the incoming clock and the PLL output clock. 

 Timequest determines that the Launch edge is the incoming clock and the Latch edge is taken as the PLL output clock, i.e. 625ps after the Launch clock edge. This is incorrect, the correct Latch edge should be the next rising edge, 1 clock cycle later. I have a slide from an Altera presentation that confirms this and the advice given is to add one clock cycle to the constraint value if the clock shift is positive.   Can someone tell me where you add an extra clock cycle, i.e. which constraint is altered for Timequest to determine the correct Launch edge and Latch edge.   Many thanks.

[Altera_Forum]

set_multicycle_path -setup -from [get_clocks clk_a] -to [get_clocks phase_shifted_clk] 2 

 That will shift the setup latch edge out one cycle, and the hold edge will move too. (In other words, you now have a positive 625ps hold requirement). Just as importantly, are you transferring data from the non-PLL clock coming in on the FPGA port to the PLL phase-shifted domain? If so, you're going to have all sorts of timing issues. What I would recommend is making the PLL have two outputs, one phase-shifted and one not, and they will have similar clock delays that cancel out, i.e. the two clocks will really be about 625ps off from each other.