Induced delay

[Altera_Forum]

I have just started learning how to use VHDL and Quartus and I use it for a Cyclone II FPGA. 

 I need to write a code , which makes my Output High after a fixed time interval , 60 seconds for example. Thus I wrote the following code for the same, however it gives me a warning that my Output pins are stuck at VCC and therefore the the Output ( an LED ) , which is ideally supposed to be OFF and glow only after 60 seconds, is always ON.  I also tried using a wait for 60 seconds statement, however that gives me a Wait statement error, saying that at WAIT UNTIL is required.   --------------------- The code is   library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all;   entity timer is port ( q : buffer bit := '0'); end entity;   architecture behaviour of timer is begin   q <= '1' after 60 sec;   end behaviour;

[Altera_Forum]

Try this one. 

 if(clk'event and clk='1') then  if count == int then  count <= 0;  else  count <= count +1; --increment counter.  if count1 > 1000 then  count1 <= 0; else if count == int then  count1 <= count1 + 1;  if count1 > 1000 then flag <= !flag ; end if; end if; end if;  There may be some typo error or some syntax error as I am not good with VHDL. But idea is to increment count1 when count reaches at value 10**6 and when count1 reaches at value 1000 it should be reset and flag signal should be inverted.

[Altera_Forum]

I made some changes and the code finally works fine. 

Thank you very much.        library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity timernew is port (clk : in std_logic; flag : out std_logic := '0' ); end timernew; architecture behave of timernew is signal count : integer:=0; signal count1: integer:=0; begin process(clk) constant int: integer :=(10**6); begin if(clk'event and clk='1') then if count = int then count <= 0; count1 <= count1 + 1; else count <= count + 1; end if; if count1 > 1000 then flag <= '1' ; else flag <= '0'; end if; end if; end process; end behave;

[Altera_Forum]

Is it possible to add a user input to determine the reset time for the same program such that after compiling or before execution of the code on the FPGA , the compiler/programmer/executor asks the user for a particular input, which is then fed into the program and the program then run. 

 So basically , the user is prompted to enter the value for x, which governs the limit for count1 .  How should I go about it ?

[Altera_Forum]

See here: 

http://www.alteraforum.com/forum/showthread.php?t=42807&p=176986#post176986

[Altera_Forum]

Sure it is! 

 How? Depends mainly on the interfaces available on your board and secondly how much coding effort you want to spend. The simplest way is using N input pins to select x among 2^N predefined values. You only need a board with some spare digital inputs, possible connected to a row of dip switches where the user select the desired value. An input method involving user prompting and directly entering the value is far far more complex and requires an advanced knowledge of hdl and fpga itself, since you'd need to implement a serial port or any other I/O interface.  This applies if you want to change x 'runtime', with a standard fpga configuration. Instead, if you want to assign the value at compilation time (so, creating a different fpga configuration for different x values), you should use tcl scripting or any other way to automate the change of the parameter whenever you start compilation.