Info: Pin qB han GND driving its datain port

Altera_Forum · ‎01-12-2015

Hello!

I am new in Altera and this is my first program.

Our task is to program the structural diagram (copying the logic diagram) of 74192 IC -- that is, SYNCHRONOUS 4-BIT UP DOWN COUNTER.

We also need to show the waveform diagram of the program and should look like what is in the datasheet.

My problem is it does not do what it should suppose to do and i've checked it many times.

I think, Info: "Pin qB has GND driving its datain port" and "upA is an undefined clock" causes the error (from the warning).

This is my code. Please help me guys :(

My reference datasheet: http://physics.gac.edu/~huber/classes/phy270/specsheets/74192.pdf

module srFlipFlop(q,q1,r,s,clk);//(q,r,s,clk,reset)

output q,q1;

input r,s,clk;

reg q,q1;

initial

begin

q=1'b0;

q1=1'b1;

end

always @(posedge clk )

begin

case({s,r})

{1'b0,1'b0}: begin q=q; q1=q1; end

{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end

{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end

{1'b1,1'b1}: begin q=1'bx; q=1'bx; end

endcase

end

endmodule

module PrelimProjectStructural(a, b, c, d, downA, upA, clr, load, bo, co, qA, qB, qC, qD);

input a, b, c, d, downA, upA, clr, load;

output bo, co, qA, qB, qC, qD;

wire notUp, notDown, notClr, notLoad;

wire wSA, wRA, wTA, wQA, wQ1A, wSB, wRB, wTB, wQB, wQ1B, wSC, wRC, wTC, wQC, wQ1C, wSD, wRD, wTD, wQD, wQ1D; //rsff

wire wAndDA, wAndDB, wAndDC, wNandDA, wNandDB, wOrDA, wOrDB;

wire wAndCA, wAndCB, wNandCA, wNandCB, wNandCC, wOrCA, wOrCB;

wire wAndBA, wAndBB, wNandBA, wNandBB, wOrBA, wOrBB;

wire wNandCo, wNandBo;

//nots

not(notUp, upA);

not(notDown, downA);

not(notClr, clr);

not(notLoad, load);

// q'

//not(wQ1A, wQA);

//not(wQ1B, wQB);

//not(wQ1C, wQC);

//not(wQ1D, wQD);

//Part D

and(wAndDA, notUp, wQC, wQB, wQA);

and(wAndDB, notUp, wQD, wQA);

and(wAndDC, wQ1C, wQ1B, wQ1A, notDown);

nand(wNandDA, notClr, notLoad, d);

nand(wNandDB, notLoad, wNandDA);

or(wOrDA, wAndDA, wAndDB, wAndDC);

or(wOrDB, ~notClr, ~wNandDB);

//Part C

and(wAndCA, notUp, wQB, wQA);

and(wAndCB, wQ1B, wQ1A, notDown, wNandCB);//

nand(wNandCA, notClr, notLoad, c);

nand(wNandCB, wQ1D, wQ1C, wQ1B);

nand(wNandCC, notLoad, wNandCA);

or(wOrCA, wAndCA, wAndCB);

or(wOrCB, ~notClr, wNandCC);

//Part B

and(wAndBA, notUp, wQ1D, wQA);

and(wAndBB, wNandCB, wQ1A, notDown);

nand(wNandBA, notClr, notLoad, b);

nand(wNandBB, notLoad, wNandBA);

or(wOrBA, wAndBA, wAndBB);

or(wOrBB, ~notClr, wNandBB);

//Part A

wire wNandAA, wNandAB, wOrAA, wOrAB;

nand(wNandAA, notClr, notLoad, a);

nand(wNandAB, notLoad,wNandAA);

or(wOrAA, notUp, notDown);

or(wOrAB, ~notClr, ~wNandAB);

//others

nand(wNandCo, notUp, wQD, wQA);

nand(wNandBo, wQ1D, wQ1C, wQ1B, wQ1A, notDown);

//flip flops

// q,q1,r,s,clk

srFlipFlop srD(.q(wQD), .q1(wQ1D), .r(wOrDB), .s(~wNandDA), .clk(~wOrDA));

srFlipFlop srC(.q(wQC), .q1(wQ1C), .r(wOrCB), .s(~wNandCA), .clk(~wOrCA));

srFlipFlop srB(.q(wQB), .q1(wQ1B), .r(wOrBB), .s(~wNandBA), .clk(~wOrBA));

srFlipFlop srA(.q(wQA), .q1(wQ1A), .r(wOrAB), .s(~wNandAA), .clk(~wOrAA));

// output bo, co, qA, qB, qC, qD;

assign bo = wNandBo;

assign co = wNandCo;

assign qA = wQA;

assign qB = wQB;

assign qC = wQC;

assign qD = wQD;

endmodule